Cypress FM4 Series - Page 47

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 47
Table 3-1 Example of PLL Multiplication Ratio Settings
Input clock
K
PLLin
N
PLLout
M
CLKPLL
4 MHz
1
4 MHz
20
320 MHz
4
80 MHz
4 MHz
1
4 MHz
30
240 MHz
2
120 MHz
4 MHz
1
4 MHz
40
320 MHz
2
160 MHz
4 MHz
1
4 MHz
50
400 MHz
2
200 MHz
5 MHz
1
5 MHz
24
240 MHz
2
120 MHz
5 MHz
1
5 MHz
30
300 MHz
2
150 MHz
5 MHz
1
5 MHz
32
320 MHz
2
160 MHz
5 MHz
1
5 MHz
40
400 MHz
2
200 MHz
6 MHz
1
6 MHz
20
240 MHz
2
120 MHz
6 MHz
1
6 MHz
25
300 MHz
2
150 MHz
6 MHz
1
6 MHz
30
360 MHz
2
180 MHz
8 MHz
1
8 MHz
20
320 MHz
2
160 MHz
8 MHz
1
8 MHz
25
400 MHz
2
200 MHz
10 MHz
1
10 MHz
8
320 MHz
4
80 MHz
10 MHz
1
10 MHz
16
320 MHz
2
160 MHz
10 MHz
1
10 MHz
15
300 MHz
2
150 MHz
10 MHz
1
10 MHz
20
400 MHz
2
200 MHz
12 MHz
1
12 MHz
10
240 MHz
2
120 MHz
12 MHz
1
12 MHz
12
288 MHz
2
144 MHz
12 MHz
1
12 MHz
15
360 MHz
2
180 MHz
15 MHz
1
15 MHz
10
300 MHz
2
150 MHz
15 MHz
1
15 MHz
12
360 MHz
2
180 MHz
16 MHz
1
16 MHz
10
320 MHz
2
160 MHz
16 MHz
2
8 MHz
25
400 MHz
2
200 MHz
19.2 MHz
2
9.6 MHz
15
288 MHz
2
144 MHz
19.2 MHz
2
9.6 MHz
20
384 MHz
2
192 MHz
20 MHz
2
10 MHz
10
200 MHz
2
100 MHz
20 MHz
2
10 MHz
20
400 MHz
2
200 MHz
30 MHz
2
15 MHz
10
300 MHz
2
150 MHz
30 MHz
2
15 MHz
12
360 MHz
2
180 MHz
40 MHz
4
10 MHz
15
300 MHz
2
150 MHz
40 MHz
4
10 MHz
20
400 MHz
2
200 MHz
48 MHz
3
16 MHz
10
320 MHz
2
160 MHz
48 MHz
4
12 MHz
12
288 MHz
2
144 MHz
48 MHz
6
8 MHz
25
400 MHz
2
200 MHz
Notes:
− For PLL characteristics, see Data Sheet of the product used.
− Set the PLLin within the value PLL input clock frequency: fPLLI shown in the Data Sheet.
− The value M  N is a multiplication ratio for the PLLin. Set this value within the range shown in the
PLL multiple rate of the Data Sheet.
− The frequency of the PLLin multiplied by M  N becomes PLLout. Set this value within the range
shown in the PLL macro oscillation clock frequency: fPLLO of the Data Sheet.
− The value of the PLLout divided by M becomes CLKPLL.
See Figure 2-1 for the configurations of PLL and divider.
− The master clock value should not be larger than the maximum value in Internal operating clock
frequency: Fcc (Base clock HCLK/FCLK) of Data Sheet