CHAPTER 4: Resets
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 163
3.1 Reset Factors
This section explains reset factors.
Power-On Reset (PONR)
A reset that is generated at power-up.
This signal is generated by detecting a rising edge of the power supply.
This signal is automatically cleared after issuing a reset.
Initializes all register settings and hardware.
bit0 (PONR) of reset factor register (RST_STR) = 1
INITX Pin Input Reset (INITX)
A reset that is externally input from a device.
This signal is generated by inputting a low level to INITX pin.
This signal is cleared by inputting a high level to INITX pin.
Initializes all register settings and hardware except the debug circuit, deep standby control block,
and RTC (some registers).
Note: The following registers are not initialized.
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
bit1 (INITX) of reset factor register (RST_STR) = 1
* The content of the on-chip SRAM is retained if a reset is asynchronously input from the INITX pin.
Low-voltage Detection Reset, External Voltage Monitoring (LVDH)
A reset that is input from a low-voltage detection circuit when a decrease in the external voltage is
detected.
This signal is generated when an external voltage is lowered than a specified level.
This signal is cleared when an external voltage is more than a specified level.
Initializes all register settings and hardware.
bit0 (PONR) of reset factor register (RST_STR) = 1
Software Watchdog Reset (SWDGR)
A reset that is input from the software watchdog timer.
This signal is generated when the software watchdog timer underflows.
This signal is automatically cleared after issuing a reset.
Initializes all register settings and hardware except the debug circuit, hardware watchdog timer
(including control registers), deep standby control block, and RTC (some registers).
Note: The following registers are not initialized.
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
bit4 (SWDT) of reset factor register (RST_STR)= 1
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