CHAPTER 4: Resets
164 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Hardware Watchdog Reset (HWDGR)
A reset that is input from the hardware watchdog timer.
This signal is generated when the hardware watchdog timer underflows.
This signal is automatically cleared after issuing a reset.
Initializes all register settings and hardware except the debug circuit, deep standby control block,
and RTC (some registers).
Note: The following registers are not initialized.
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
bit5 (HWDT) of reset factor register (RST_STR) = 1
Clock Failure Detection Reset (CSVR)
A reset that is input when the main or sub crystal oscillator being monitored fails.
This signal is generated when a clock failure is detected in the main or sub crystal oscillator.
This signal is automatically cleared after issuing a reset.
Initializes all register settings and hardware except the debug circuit , clock failure detection
circuit (some registers), deep standby control block, and RTC (some registers).
Note: The following registers are not initialized.
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
bit6 (CSVR) of reset factor register (RST_STR) = 1
bit1 (SCMF) or bit0 (MCMF) of CSV status register (CSV_STR) = 1
Note: For details on the CSV_STR, see Chapter "Clock supervisor".
Anomalous Frequency Detection Reset (FCSR)
A reset that is input when an anomalous frequency is detected in the main crystal oscillator.
This signal is generated when the frequency of the main crystal oscillator is outside of any given
setting.
This signal is automatically cleared after issuing a reset.
Initializes all register settings and hardware except the debug circuit, anomalous frequency
detection (some registers), deep standby control block, and RTC (some registers).
Note: The following registers are not initialized.
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
bit7 (FCSR) of reset factor register (RST_STR) = 1
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