Cypress FM4 Series - Page 165

CHAPTER 4: Resets
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 165
Software Reset (SRST)
A reset that is generated when an access to the reset control register occurs.
Generated by
This signal is generated by a write to the Cortex-M4 internal reset control register
(SYSRESETREQ bit).
Cleared by
This signal is automatically cleared after issuing a reset.
Initialization
target
Initializes all register settings and hardware except the following:
Functions and registers that are not initialized by a software reset
− Debug circuit
− Deep standby control block
− Some registers of RTC
− Some registers related to clock control (Peripheral clock stop register can be initialized.)
− Part of registers that control software and hardware watchdog timers
− Part of registers in the clock failure detection circuit
− Part of registers that detect an anomalous frequency
− Part of registers for CR trimming
− Reset factor register (RST_STR)
− bit15 to bit8 of low-voltage detection voltage setting register (LVD_CTL)
− RTC mode control register (PMD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
Flag
bit8 (SRST) of reset factor register (RST_STR) = 1
Deep standby transition reset (DSTR)
This reset occurs when transiting to deep standby mode.
Generated by
This signal is generated by transiting to deep standby mode
Cleared by
This signal is cleared by returning from deep standby mode
Initialization
target
Initializes all register settings and hardware except the following:
Functions and registers that are not initialized by a deep standby transition reset.
− Deep standby control block
− Some registers of RTC
− Some registers of GPIO
− Low-voltage detection circuit register
− RTC mode control register (PMD_CTL)
− Deep standby return factor registers 1 and 2 (WRFSR, WIFSR)
− Deep standby return enable register (WIER)
− WKUP pin input level register (WILVR)
− Deep Standby RAM Retention Register (DSRAMR)
− Backup registers from 01 to 16 (BUR01 to BUR16)
Flag
The bit of either deep standby return factor register 1 or 2 (WRFSR, WIFSR) is "1".
Note: The bit that becomes "1" differs by return factors.
Notes:
− For Cortex-M4 internal reset control register (SYSRESETREQ) that controls the software reset,
see "Cortex-M4 Devices Generic User Guide ".
− The reset factor register that can determine the occurrence of each reset factor is initialized only
by power-on reset.