CHAPTER 2-1: Clock
48 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.4 Oscillation Stabilization Wait Time
This section explains the oscillation stabilization wait time.
An oscillation stabilization wait time is required if the source clock is not in a stable operating state. During
the oscillation stabilization wait time, internal and external clocks stop the supply, only the internal time
counter operates to wait until the stabilization wait time passes, a time value set in the Clock Stabilization
Wait Time Register (CSW_TMR) or PLL Clock Oscillation Stabilization Wait Time Setup Register
(PSW_TMR). When the wait time has been passed, the corresponding oscillator is ready to operate, and
the clock can be used as a master clock.
Setting the Oscillation Stabilization Wait Time
− Main clock (CLKMO)
Set the stabilization wait time of the main clock using the Clock Stabilization Wait Time Register
(CSW_TMR). The set time value is counted by CLKHC.
− Sub clock (CLKSO)
Set the stabilization wait time of the sub clock using the Clock Stabilization Wait Time Register
(CSW_TMR). The set time value is counted by CLKLC.
− Main PLL clock
Configure the following settings using the PLL Clock Oscillation Stabilization Wait Time Setup
Register (PSW_TMR). The set time value is counted by CLKHC.
− Selecting the PLL input clock
Setting the main PLL clock stabilization wait time
Cause of Waiting for Oscillation Stability
− After the oscillation is enabled via software
If the PLLE, SOSCE, and MOSCE bits of the System Clock Mode Control Register (SCM_CTL)
are set to 1, each relevant oscillator waits during the oscillation stabilization wait time.
− When returning to watch counter interrupt, RTC interrupt, and external interrupt from RTC mode
It returns to the clock mode before RTC mode by watch counter interrupt, RTC interrupt, and
external interrupt. Since a source clock other than the sub clock is stopped in RTC mode,
hardware of a source clock other than the sub clock waits for the oscillation stabilization wait time
automatically.
− When returning from stop mode using an external interrupt
The status returns to clock mode, a state before stop mode, using an external clock. During stop
mode, all source clocks stop and, therefore, the hardware automatically waits during the
oscillation stabilization wait time.
− After PLL operation is enabled
After PLL operation is enabled, the PLL oscillation stabilization wait time is waited.
Notes:
− Each set value of the oscillation stabilization wait time must be changed before the clock is
enabled.
− After software reset, the oscillation stabilization wait time is not applied.
− In the stabilization wait time for main clock, sub clock and main PLL clock, the high-speed CR
clock (CLKHC) counts the clock as set in the Stabilization Wait Time Setup Registers. The
oscillation stabilization wait completion flag will be activated when the counting is complete, so
these wait times are independent of each oscillator statuses. The oscillation stabilization wait
time may be completed before oscillator stabilization if the setting of the oscillation stabilization
wait time is too short.
− As the stabilization wait times for main clock and sub clock oscillators depend on the type of the
oscillator (crystal, ceramics, etc.), proper oscillation stabilization wait time must be chosen for the
oscillator to be used.
− Set the PLL oscillation stabilization wait time by referring to PLL Clock LOCKUP Time of the
electric characteristics described in "Data Sheet" of the product used.
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