Cypress FM4 Series - Dqmskclr[N] Register

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 571
5.12 DQMSKCLR[n] Register
The DQMSKCLR[n] Register is a register for clearing the DQMSK[n] Register.
Register configuration
Address
+0x90
Field
DQMSKCLR[31:0]
+0x94
Field
DQMSKCLR[63:32]
+0x98
Field
DQMSKCLR[95:64]
+0x9C
Field
DQMSKCLR[127:96]
+0xA0
Field
DQMSKCLR[159:128]
+0xA4
Field
DQMSKCLR[191:160]
+0xA8
Field
DQMSKCLR[223:192]
+0xAC
Field
DQMSKCLR[255:224]
Attribute
(applicable to all areas)
W
Initial value
(applicable to all areas)
0x00000000
Register function
The DQMSKCLR[n] Register is a write-only register. When the DSTC is in the standby state, no write
access can be made to this register.
If "1" is written to this register, the DQMSK[n] Register is cleared to "0". Clearing the DQMSK[n] Register
makes a suppressed HW transfer start immediately. Therefore, complete the setup of the peripheral for
that suppressed transfer and the setup of the DES before clearing the DQMSK[n] Register.
bit[255:0] DQMSKCLR[255:0] (DMA request mask clear)
Access
Function
Writing "0"
No operation is executed.
Writing "1"
Clears the DQMSK[n] Register to "0".
Reading
All bits in this register always read "0".
If the DSTC installed in a product supports HW-128 channels, the DQMSKCLR[255:128] bits are a
reserved area whose value is fixed at "0".
If the DSTC installed in a product supports HW-64 channels, the DQMSKCLR[255:64] bits are a reserved
area whose value is fixed at "0".