Cypress FM4 Series - Overview of DSTC

CHAPTER 11: DSTC
504 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Overview of DSTC
This section provides an overview of the DSTC (Descriptor System data Transfer Controller).
Overview
The DSTC (Descriptor System data Transfer Controller), like the DMAC, is a function block that can
transfer data at high speed bypassing the CPU. Using the Descriptor (to be called DES later in this
document) System Method, it directly accesses memory or a peripheral device according to the content
specified in a DES created on the memory, and executes a data transfer operation.
One set of transfer control details (basic transfer settings, number of transfers, transfer source address,
transfer destination address) is specified in one DES. The DSTC can multiple DES individually and can
build up to 1024 transfer channels.
The data transfer operation can be started by one of the following three methods: direct start by the CPU
(software start), start by an interrupt signal from a peripheral device (hardware start), and the Chain Start
Function.
The chain start function executes a transfer according to the current DES, and then starts a new transfer
according to the succeeding DES or according to the current DES again. It can be specified in the DES
whether to use the Chain Start Function. With the chain start function, the DSTC can incorporate other
types of transfer specified in multiple DES into a single start trigger (software start / hardware start) in the
start DES, and execute such types of transfer together. In addition, it can also divide a transfer operation
specified in a DES into several transfer operations and then execute them.
The DSTC has two reload functions for the transfer address and for the transfer count counter (the
InnerRelaod Function that during a transfer makes the value return to the one at the start of the transfer,
the OuterReload Function that at the end of a transfer makes the value return to the one at the start of the
transfer). The two reload functions facilitate the control of repeating the same transfer operation.
The DSTC can notify the CPU of the normal end or abnormal end of a transfer operation as an interrupt.
It can control how an internal clock is stopped in a standby mode (low power consumption mode).
The DSTC has a dedicated bus, which is independent of the CPU bus, and has a configuration enabling it
to execute a transfer operation when the CPU bus is being accessed.
The configuration of the dedicated bus conforms to the system bus (AHB) and supports a 32-bit address
space (4 Gbyte).
Number of Channels Supported in Hardware Transfer of DSTC
For a product equipped with the DSTC, if the DSTC supports 256 channels, it can use all hardware
transfer channels from channel 0 to channel 255. If the DSTC supports 128 channels, it cannot use
channel 128 to channel 255. If the DSTC supports 64 channels, it cannot use channel 64 to channel 255.