CHAPTER 2-1: Clock
38 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Clock Generation Unit Overview
This section provides an overview of the clock generation unit.
The clock generation unit generates various types of clocks used to operate the MCU.
Source clock is the generic name for external and internal oscillation clocks of this MCU.
The following five types of clocks are source clocks:
Main clock (CLKMO)
Sub clock (CLKSO)
High-speed CR clock (CLKHC)
Low-speed CR clock (CLKLC)
Main PLL clock (CLKPLL)
Select one from the source clocks. In this chapter, the selected clock is referred to as the master clock.
The master clock is a source of internal bus clocks used to operate this MCU.
Dividing the master clock frequency can generate a base clock. In addition, dividing the base clock can
generate each bus clock.
In this chapter, the base clock and bus clocks are referred to as internal bus clocks. The following five
types of clocks are internal bus clocks:
Base clock (FCLK/HCLK)
APB0 bus clock (PCLK0)
APB1 bus clock (PCLK1)
APB2 bus clock (PCLK2)
TRACE clock (TPIUCLK)
In addition to source clocks, the master clock, and internal bus clocks, the following clocks are provided:
USB clock
USB/Ethernet clock
CAN prescaler clock
I
2
S clock
GDC clock
Software watchdog timer count clock
The following shows the features of the clock generation unit.
It can set the oscillation stabilization wait time of the main clock (CLKMO).
It can set the interrupt which generates at completing the oscillation stabilization wait time of the main
clock (CLKMO).
It can set the oscillation stabilization wait time of the sub clock (CLKSO).
It can set the interrupt which generates at completing the oscillation stabilization wait time of the sub
clock (CLKSO).
It can set the oscillation stabilization wait time of the main PLL clock (CLKPLL).
It can set the interrupt which generates at completing the oscillation stabilization wait time of the main
PLL clock (CLKPLL).
It can set the PLL multiplication ratio.
It can select the master clock.
It can set the frequency division ratio of each internal bus clock frequency.
It can select run or stop of the APB1 and APB2 bus clocks.
It can set the frequency division ratio of the software watchdog timer count clock frequency.
It can set run/stop of the software watchdog timer count clock.
It can set the watchdog timer count operation in debug mode.
It includes registers for enabling clock-related interrupts, checking interrupt status, and clearing interrupt
factors.
It can use clock gear function. (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products)
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