Cypress FM4 Series - Configuration of CPU Operation Modes

CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 195
2. Configuration of CPU Operation Modes
This section explains the configuration of CPU operation modes.
CPU Operation Mode Transition Diagram
Figure 2-1 shows the CPU operation mode transition diagram.
Figure 2-1 CPU Operation Mode Transition Diagram
Power-on
Initialization
Power-on reset
High speed CR oscillation
stabilization wait
Low speed CR oscillation
stabilization wait
High speed CR mode
Main mode
PLL mode
Low speed CR mode
Sub mode
(1)
(2)
(3)
(4)
(5)
(1) Power-on reset
(2) Release of power-on reset
(3) End of oscillation stabilization wait
(4) Transition to main mode (MOSCE = 1, RCS = 001)
(5) Transition to high speed CR mode (RCS = 000)
(6)
(6) Transition to low speed CR mode (RCS = 100)
(5)
(7) Transition to sub mode (SOSCE= 1, RCS = 101)
(4)
(6)
(7)
(5)
(8) Transition to PLL mode (PLLE = 1, RCS = 010)
(8)
(4)
(9) (9)
(9) Reset (Except software reset)
(4)
(7)
(6)(7)
(8)
(7)
(8)
(8)
(5)
(6)
 High speed CR mode
In this mode, the high speed CR oscillator clock is used as the master clock.
 Main mode
In this mode, the main oscillator clock is used as the master clock.
 Low speed CR mode
In this mode, the low speed CR oscillator clock is used as the master clock.
 Sub mode
In this mode, the sub oscillator clock is used as the master clock.
 PLL mode
In this mode, the PLL clock is used as the master clock.