Cypress FM4 Series - APB1 Prescaler Register (APBC1_PSR)

CHAPTER 2-1: Clock
64 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.5 APB1 Prescaler Register (APBC1_PSR)
The APBC1_PSR sets the APB1 bus clock frequency division.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
APBC1EN
Reserved
APBC1RST
Reserved
APBC1
Attribute
R/W
-
R/W
-
R/W
Initial value
1
-
0
-
00
Register functions
[bit7] APBC1EN: APB1 clock enable bit
bit
Description
0
Disables PCLK1 output
1
Enables PCLK1 output [Initial value]
[bit6:5] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit4] APBC1RST: APB1 bus reset control bit
bit
Description
0
APB1 bus reset, inactive [Initial value]
1
APB1 bus reset, active
[bit3:2] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit1:0] APBC1: APB1 bus clock frequency division setting bits
bit1
bit0
Description
0
0
1/1 [Initial value]
0
1
1/2
1
0
1/4
1
1
1/8
Note:
− This register is not initialized by software reset.