Cypress FM4 Series - Operation of the Programmable CRC

CHAPTER 19: Programmable CRC
934 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
2.2 Operation of the Programmable CRC
This section explains the functions of the programmable CRC and computing operation based on the
block diagram in Figure 2-1.
CRC computing is performed in the LFSR (Linear Feedback Shift Register) block in the block diagram.
Specify the generator polynomial value of CRC computing to the PRGCRC_POLY register before
computing starts. CRC computing can be performed at arbitrary length up to 32-bit length. The initial
values of CRC computing can be arbitrarily specified with the PRGCRC_SEED register. The value
operated with bitwise XOR for results of CRC computing can be arbitrarily specified with the
PRGCRC_FXOR register.
CRC computing starts performing by writing input data into the PRGCRC_WR register. The data input
from CPU is converted in the input format conversion block, and then it is input to LFSR. The size of input
data can be selected from 8-bit/16-bit/24-bit/32-bit. The format (bit order/byte order) conversion of input
data can be selected from four types. Specify the settings with SZ[1:0] and FI[1:0] in the PRGCRC_CFG
register respectively.
Table2-2 shows operation example of input format conversion of 16-bit data.
Table2-2 Operation Example of Input Data Format Conversion
PRGCRC_WR
Write Value
(Hexadecimal)
PRGCRC_CFG.FI
Input Format Conversion
Operation
Input Data to LFSR
(binary)
(Left Value is Input First)
0x12 0x35
(Byte-A) (Byte-B）
00
（MSB-first / Big endian）
Bit order: from left to right
Byte order: Byte-A, Byte-B
00010010 00110101
01
（MSB-first / Little endian）
Bit order: from left to right
Byte order: Byte-B, Byte-A
00110101 00010010
10
（LSB-first / Big endian）
Bit order: from right to left
Byte order: Byte-A, Byte-B
01001000 10101100
11
（LSB-first / Little endian）
Bit order: from right to left
Byte order: Byte-B, Byte-A
10101100 01001000
When CRC computing is started, "1" is set to LOCK of the PRGCRC_CFG register. When the computing
is completed, LOCK is reset to "0". The status of CRC computing, running or not running, can be
identified by reading this status register from CPU. The time from the writing of input data to the
completion of computing is determined depending on the SZ[1:0] value of the PRGCRC_CFG register.
Table2-3 shows the number of clock cycles required for computing process.
Table2-3 Number of Clocks for CRC Computing Process
SZ[1:0]
Number of Clock Cycles Required for
Computing Process
00
10
01
18
10
26
11
34
After CRC computing process is completed, the next input data can be written. When the next input data
is written, CRC computing is continuously processed after the computing results currently held in LFSR.
The CRC computing results stored in LFSR can be read from the PRGCRC_RD register. The format (bit
order/byte order) conversion of output data can be selected from four types. Specify the setting with
FO[1:0] in the PRGCRC_CFG register. As shown in the block diagram, the output format conversion is