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Cypress FM4 Series - Page 935

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CHAPTER 19: Programmable CRC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 935
performed at first, the value specified with the PRGCRC_FXOR register is operated with bitwise XOR,
and then the value is stored in the PRGCRC_RD register.
Table2-4 shows operation example of output format conversion of 16-bit data.
Table2-4 Operation Example of Output Data Format Conversion
Output Data from LFSR
(binary)
(Left value is output first)
PRGCRC_CFG.FO
Output Format Conversion Operation
PRGCRC_RD
Read Value
(Hexadecimal)
10011010 10111100
00
MSB-first / Big endian
Bit order: from left to right
Byte order: Byte-A, Byte-B
0x9A 0xBC
(Byte-A) (Byte-B)
01
MSB-first / Little endian
Bit order: from left to right
Byte order: Byte-B, Byte-A
0xBC 0x9A
(Byte-B) (Byte-A)
10
LSB-first / Big endian
Bit order: from right to left
Byte order: Byte-A, Byte-B
0x59 0x3D
(Byte-A) (Byte-B)
11
LSB-first / Little endian
Bit order: from right to left
Byte order: Byte-B, Byte-A
0x3D 0x59
(Byte-B) (Byte-A)
Table2-5 shows examples of relations among CRC values held in LFSR (*1), values converted with the
output format conversion (*2), PRGCRC_FXOR setting values (*3), and values stored in the
PRGCRC_RD register (*4).
Table2-5 Operation Example of Output Data Format Conversion
CRC
Length
CRC Value of LFSR (*1)
(Left value is output first)
FO
Output Format
Converted Value (*2)
PRGCRC_FXOR
Setting Value (*3)
PRGCRC_RD
Stored Value (*4)
32
0x 9ABC DEF1
00
0x 9ABC DEF1
0x FFFF FFFF
0x 6543 210E
01
0x F1DE BC9A
0x FFFF FFFF
0x 0E21 4365
10
0x 593D 7B8F
0x FFFF FFFF
0x A6C2 8470
11
0x 8F7B 3D59
0x FFFF FFFF
0x 7084 C2A6
21
0x 9ABC D800
00
0x 9ABC D800
0x FFFF F800
0x 6543 2000
01
0x 00D8 BC9A
0x 00F8 FFFF
0x 0020 4365
10
0x 593D 1B00
0x FFFF 1F00
0x A6C2 0400
11
0x 001B 3D59
0x 001F FFFF
0x 0004 C2A6
16
0x 9ABC 0000
00
0x 9ABC 0000
0x FFFF 0000
0x 6543 0000
01
0x 0000 BC9A
0x 0000 FFFF
0x 0000 4365
10
0x 593D 0000
0x FFFF 0000
0x A6C2 0000
11
0x 0000 3D59
0x 0000 FFFF
0x 0000 C2A6
13
0x 9AB8 0000
00
0x 9AB8 0000
0x FFF8 0000
0x 6540 0000
01
0x 0000 B89A
0x 0000 F8FF
0x 0000 4065
10
0x 591D 0000
0x FF1F 0000
0x A602 0000
11
0x 0000 1D59
0x 0000 1FFF
0x 0000 02A6
1
0x 8000 0000
00
0x 8000 0000
0x 8000 0000
0x 0000 0000
01
0x 0000 0080
0x 0000 0080
0x 0000 0000
10
0x 0100 0000
0x 0100 0000
0x 0000 0000
11
0x 0000 0001
0x 0000 0001
0x 0000 0000
Each time computing is completed, the computing result is stored in the PRGCRC_RD register. As shown
in the block diagram, the PRGCRC_FXOR register value only affects the value stored in the
PRGCRC_RD register, and it does not affect the computing result stored in LFSR. After writing all input
data required is completed and the last CRC computing is completed, the CRC computing result with
reflection of the PRGCRC_FXOR register value is acquired when the PRGCRC_RD register is read.
The latest CRC computing result is stored in LFSR. To start another CRC computing, be sure to write the
initial values to the PRGCRC_SEED register to reset the initial values of the LFSR.

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