Cypress FM4 Series - PLL Clock Gear Control Register (PLLCG_CTL)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 77
5.17 PLL Clock Gear Control Register (PLLCG_CTL)
The PLLCG_CTL sets the clock gear.
This register is equipped in TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products.
Register configuration
bit
23
22
21
20
19
18
17
16
Field
PLLCGLP
Attribute
R/W
Initial value
11111111
bit
15
14
13
12
11
10
9
8
Field
PLLCGSTP
PLLCGSSN
Attribute
R/W
R/W
Initial value
00
000000
bit
7
6
5
4
3
2
1
0
Field
PLLCGSTS
Reserved
PLLCGSTR
PLLCGEN
Attribute
R
-
R/W
R/W
Initial value
00
-
0
0
Register functions
[bit23:16] PLLCGLP : PLL clock gear step loop configuration bits
bit23:16
Description
00000000
PLL clock gear step loop sets to 1 loop
00000001
PLL clock gear step loop sets to 2 loops
00000010
PLL clock gear step loop sets to 3 loops
・
・
11111101
PLL clock gear step loop sets to 254 loops
11111110
PLL clock gear step loop sets to 256 loops
11111111
PLL clock gear step loop sets to 256 loops [Initial value]
[bit15:14] PLLCGSTP : PLL clock gear step configuration bits
bit15
bit14
Description
0
0
PLL clock gear step width sets to 1 step [Initial value]
0
1
PLL clock gear step width sets to 2 steps
1
0
PLL clock gear step width sets to 3 steps
1
1
PLL clock gear step width sets to 4 steps
[bit13:8] PLLCGSSN : PLL clock gear start step number configuration bits
bit13:8
Description
000000
PLL clock gear start step number sets to STEP0 [Initial value]
000001
PLL clock gear start step number sets to STEP1
000010
PLL clock gear start step number sets to STEP2
・
・
111101
PLL clock gear start step number sets to STEP61
111110
PLL clock gear start step number sets to STEP62
111111
PLL clock gear start step number sets to STEP63