Cypress FM4 Series - Page 78

CHAPTER 2-1: Clock
78 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit7:6] PLLCSTS : PLL clock gear start bits
bit7
bit6
Description
0
0
Not used clock gear [Initial value]
Stop clock gear operation at minimum frequency when clock gear is enabled.
0
1
Gear up operation
1
0
Stop clock gear operation at maximum frequency when clock gear is enabled.
1
1
Gear down operation
[bit5:2] Reserved: Reserved bits
0b0000 is read from these bits.
Set these bits to 0b0000 when writing.
[bit1] PLLCGSTR : PLL clock gear start bit
bit
Description
0
PLL clock gear is no operation
1
Start clock gear operation
[bit0] PLLCGEN : PLL clock gear enable bit
bit
Description
0
PLL clock gear disable
1
PLL clock gear enable
Note:
− PLLCGLP, PLLCGSTP, PLLCGSSN, PLLCGEN have to be set before PLL clock enable setting
(SM_CTL.PLLE=1).
− PLLCGSTR is cleared by hardware after clock gear operation finishes.