CHAPTER 2-1: Clock
50 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.6 Clock Gear Function
The clock gear function is equipped in TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products.
Due to drastic frequency difference, switching from the main clock to PLL clock or from PLL clock to the
main clock cause huge fluctuation of power supply current.
By utilizing the clock gear circuit, it can gradually shift the operating frequency from high-frequency to
low-frequency or from low-frequency to high-frequency. So it can reduce sudden surge of power supply
current.
Clock Gear Control
The gear clock is output from clock gear circuit. Figure 3-1 shows the gear clock wave.
The frequency of the gear clock is gradually changed by the steps of main PLL clock.
When the step configuration (PLLCG_CTL.PLLCGSTP[1:0]) is smaller or the step loop configuration
(PLLCG_CTL.PLLCGLP[7:0]) is bigger, the frequency of the gear clock can be more slowly changed.
The control unit with a single 64 input clock cycle of the clock gear circuit, the following control can be set
by a variety of gear clock.
− Start step configuration (PLLCG_CTL.PLLCGSSN[6:0]))
The start step configuration sets the starting step of the gear clock output. It is possible of 0 to 63.
For example, in the case of setting to 1, the starting step of the clock gear output is STEP0.
− Step loop configuration (PLLCG_CTL.PLLCGLP[7:0])
The step loop configuration sets the loop of each step of the gear-up and gear-down.
It is possible of 1 to 256.
For example, in the case of setting to 1, the step loop of the each step is 2 loops.
− Step configuration (PLLCG_CTL.PLLCGSTP[1:0])
The step configuration sets the step width of the gear-up and gear-down. It is possible of 1 to 4.
For example, in the case of setting to 0, the step counts up by one in the gear-up.
(STEP0→STEP1→STEP2)
Figure 3-1 Clock Gear Configuration and Gear Clock Output
To Next Page
Loading...
