Cypress FM4 Series - Page 51

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 51
Gear-up Procedure
The gear-up procedure explains below.
1. The step loop configuration (PLLCG_CTL.PLLCGLP[7:0]), the step configuration
(PLLCG_CTL.PLLCGSTP[1:0]) and the start step configuration (PLLCG_CTL.PLLCGSSN[6:0])
set the gear step you want to use.
And the clock gear enable bit (PLLCG_CTL.PLLCGEN) is set to be enabled (1).
2. PLL oscillation is set to be enabled (1).
3. After completion of oscillation stabilization standby timer, the initial step clock, selected to the start
step configuration (PLLCG_CTL.PLLCGSSN[6:0]) is output.
4. Master clock select to PLL clock.
5. The clock gear start bit (PLLCG_CTL.PLLCGSTR) is set to 1.
Then the gear-up starts, and the clock gear status (PLLCG_CTL.PLLCGSTS[1:0]) is changed 00
to 01.
6. Please poll PLLCG_CTL.PLLCGSTS[1:0] until the value is changed 10.
7. When the clock is the maximum step, the clock gear status (PLLCG_CTL.PLLCGSTS[1:0]) is
changed 01 to 10. Then the gear-up stops and the master clock is output to the frequency of the
main PLL clock.
In this time, PLLCGSTR is cleared by hardware after clock gear operation finishes.
Note:
− During the gear-up, it polls PLLCG_CTL.PLLCGSTS[1:0] and please wait until the clock shows
the maximum frequency stopped state(10).
Gear-down Procedure
The gear-down procedure explains below.
1. The clock gear start bit (PLLCG_CTL.PLLCGSTR) is set to 1.
Then the gear-down starts, and the clock gear status (PLLCG_CTL.PLLCGSTS[1:0]) is changed
10 to 11.
The step loop configuration (PLLCG_CTL.PLLCGLP[7:0]), the step configuration
(PLLCG_CTL.PLLCGSTP[1:0]) and the start step configuration (PLLCG_CTL.PLLCGSSN[6:0])
set the gear step of the gear-up setting.
2. Please poll PLLCG_CTL.PLLCGSTS[1:0] until the value is changed 00.
3. When the clock is the minimum step, the clock gear status (PLLCG_CTL.PLLCGSTS[1:0]) is
changed 11 to 00. Then the gear-down stops and the master clock is output to the frequency
selected the start step configuration (PLLCG_CTL.PLLCGSSN[6:0]).
In this time, PLLCGSTR is cleared by hardware after clock gear operation finishes.
4. Mater clock is selected to the hopeful clock.
Note:
− During the gear-down, it polls PLLCG_CTL.PLLCGSTS[1:0] and please wait until the clock
shows the minimum frequency stopped state(00).