CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 469
4.1 Overview of DMAC Control
This section provides an overview of DMAC control.
The control register of each channel of DMAC has EB (individual-channel operation enable bit) and PB
(individual-channel pause bit). By manipulating these bits, the start of DMA transfer operation (operation
enabled), the forced termination of transfer operation (operation disabled) and the pause of transfer
operation can be controlled by channel. The control register also has DE (all-channel operation enable
bit) and DH (all-channel pause bit), which allow the transfer operations of all channels to be controlled at
once.
Each channel is originally in the operation-prohibited state (Disable state) in which the transfer content
(the address of the transfer source, the address of the transfer destination, the transfer data width, the
number of transfers, the transfer mode, etc.) are specified for each channel to its configuration register.
Then, the transfer operations are controlled by writing to EB, PB, DE and DH to instruct the transfer
operations to be started or paused.
Once each channel completes its transfer, it sets the end code to SS (Stop Status) to give the notification
of its stop state. An interrupt can be generated upon the completion of transfer. After the transfer ends,
each channel clears EB and PB and returns to the operation-prohibited state (Disable state).
The following sections describe the operations of and control procedures for DMA transfer by software
request and hardware DMA transfer by transfer request from Peripherals.
The following terms are used in the explanations as instructions from CPU, which refer to writing the
following values to the EB, PB, DE and DH bits.
− Instruction to enable individual-channel operation (write EB=1, PB=0)
− Instruction to disable individual-channel operation (write EB=0)
− Instruction to pause individual-channel operation (write EB=1, PB=1)
− Instruction to enable all-channel operation (write DE=1, DH=0000)
− Instruction to disable all-channel operation (write DE=0)
− Instruction to pause all-channel operation (write DE=1, DH!=0000)
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