Cypress FM4 Series - System Clock Mode Status Register (SCM_STR)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 61
5.2 System Clock Mode Status Register (SCM_STR)
The SCM_STR indicates a clock selected for the master clock and a waiting state for clock oscillation
stability.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
RCM[2:0]
PLRDY
SORDY
Reserved
MORDY
Reserved
Attribute
R
R
R
-
R
-
Initial value
000
0
0
-
0
-
Register functions
[bit7:5] RCM[2:0]: Master clock selection bits
bit7
bit6
bit5
Description
0
0
0
High-speed CR clock [Initial value]
0
0
1
Main clock
0
1
0
Main PLL clock
0
1
1
Setting is prohibited
1
0
0
Low-speed CR clock
1
0
1
Sub clock
1
1
0
Setting is prohibited
1
1
1
Setting is prohibited
[bit4] PLRDY: PLL oscillation stable bit
bit
Description
0
In a stabilization wait or an oscillation stop state [Initial value]
1
In a stable state
[bit3] SORDY: Sub clock oscillation stable bit
bit
Description
0
In a stabilization wait or an oscillation stop state [Initial value]
1
In a stable state
[bit2] Reserved: Reserved bit
0 is read from this bit.
[bit1] MORDY: Main clock oscillation stable bit
bit
Description
0
In a stabilization wait or an oscillation stop state [Initial value]
1
In a stable state
[bit0] Reserved: Reserved bit
0 is read from this bit.
Notes:
− This register is not initialized by software reset.
− When RTCE bit (PMD_CTL:RTCE) of RTC mode control register (PMD_CTL) is 1, it becomes a
sub clock oscillation enable state regardless of the SOSCE bit and SORDY bit values.
− Writing 1 to RTCE bit (PMD_CTL:RTCE) is enabled only when SORDY bit is 1.