Cypress FM4 Series - Clock Generation Unit Configuration;Block Diagram

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 39
2. Clock Generation Unit Configuration/Block Diagram
This section explains configuration of the clock generation unit.
Source Clocks
Source clock is the generic name for external and internal oscillation clocks of this MCU. The following
five types of clocks are source clocks:
 Main clock (CLKMO)
CLKMO is generated by connecting a crystal oscillator etc. to the main clock oscillation pins (X0, X1), or
input using an external clock.
 Sub clock (CLKSO)
CLKSO is generated by connecting a crystal oscillator etc. to the sub clock oscillator pins (X0A, X1A), or
input using an external clock.
 High-speed CR clock (CLKHC)
CLKHC is an output clock for the high-speed CR oscillator.
 Low-speed CR clock (CLKLC)
CLKLC is an output clock for the low-speed CR oscillator.
Note:
− The low-speed CR clock is a clock after a prerscaler.
For details on the low-speed CR clock prescaler, see Chapter "Low-speed CR Clock Prescaler".
 Main PLL clock (CLKPLL)
CLKPLL is generated by multiplying the main clock (CLKMO) or high-speed CR clock (CLKHC) using the
PLL Clock Multiplication Circuit (PLL Oscillation Circuit).
Master Clock
The signal selected from source clocks are referred to as the master clock.
The master clock is a source for all bus clocks.
Notes:
− See 1. Notes when high-speed CR is used for the master clock in B. List of Notes when you use
the following clock for the master clock.
− High-speed CR clock
− Main PLL clock (When selecting high-speed CR clock for the input clock of PLL)
− The master clock value should not be larger than the maximum value in Internal operating clock
frequency: Fcc(Base clock HCLK/FCLK)of AC Specifications in Data Sheet.