EasyManua.ls Logo

Cypress FM4 Series - Page 40

Cypress FM4 Series
1102 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
CHAPTER 2-1: Clock
40 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Internal Bus Clocks
The following signals are bus clocks generated internally.
Base clock (HCLK/FCLK)
HCLK and FCLK are collectively called the base clock. Both HCLK and FCLK are supplied to the CPU.
HCLK is a clock for macro connected to the AHB bus.
The clock frequency can be set to between 1/1 and 1/16 frequency of the master clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop
mode.
In sleep mode, the CPU stops the supply of HCLK while continuing the supply of FCLK.
APB0 bus clock (PCLK0)
PCLK0 is a clock for peripheral macro connected to the APB0 bus.
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop
mode.
APB1 bus clock (PCLK1)
PCLK1 is a clock for peripheral macro connected to the APB1 bus.
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop
mode.
The supply of the clock can be also stopped by setting a register.
APB2 bus clock (PCLK2)
PCLK2 is a clock for peripheral macro connected to the APB2 bus.
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop
mode.
The supply of the clock can be also stopped by setting a register.
TPIU clock (TPIUCLK)
TPIUCLK is a clock for TRACE.
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode and deep standby stop
mode.
This clock output is enabled only for the products equipped with ETM.
Clocks Other than Source Clocks and Internal Bus Clocks
USB clock
This clock generates a clock at 48 MHz, used by USB communication.
It sets the PLL oscillator for USB to generate a USB clock.
This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop
mode.
This clock can be set independently regardless of the frequency of the master clock.
For USB clock operation settings, see Chapter USB clock generation in Communication Macro Part.

Table of Contents

Related product manuals