Cypress FM4 Series - CSV Control Register (CSV_CTL)

CHAPTER 3: Clock Supervisor
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 151
6.1 CSV control register (CSV_CTL)
The CSV_CTL register configures the control of CSV function.
Register configuration
bit
15
14
13
12
11
10
9
8
Field
Reserved
FCD
Reserved
FCSRE
FCSDE
Attribute
-
R/W
-
R/W
R/W
Initial value
-
111
-
0
0
bit
7
6
5
4
3
2
1
0
Field
Reserved
SCSVE
MCSVE
Attribute
-
R/W
R/W
Initial value
-
1
1
Register functions
[bit15] Reserved: Reserved bit
"0" is read from this bit.
Set this bit to "0" when writing.
[bit14:12] FCD: FCS count cycle setting bits
bit14:12
Description
When 000 is written
Setting is prohibited
When 001 is written
When 010 is written
When 011 is written
When 100 is written
When 101 is written
1/256 frequency of high-speed CR oscillation
When 110 is written
1/512 frequency of high-speed CR oscillation
When 111 is written
1/1024 frequency of high-speed CR oscillation [Initial value]
When read
The register value is read.
[bit11:10] Reserved: Reserved bits
"0b00" is read from these bits.
Set these bits to "0b00" when writing.
[bit9] FCSRE: FCS reset output enable bit
bit
Description
When 0 is written
The FCS reset is disabled [Initial value]
When 1 is written
The FCS reset is enabled
When read
The register value is read.
[bit8] FCSDE: FCS function enable bit
bit
Description
When 0 is written
The FCS function is disabled [Initial value]
When 1 is written
The FCS function is enabled.
When read
The register value is read.