Cypress FM4 Series - Page 152

CHAPTER 3: Clock Supervisor
152 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit7:2] Reserved: Reserved bits
"0b000000" is read from these bits.
Set these bits to "0b000000" when writing.
[bit1] SCSVE: Sub CSV function enable bit
bit
Description
When 0 is written
The sub CSV function is disabled
When 1 is written
The sub CSV function is enabled. [Initial value]
When read
The register value is read.
[bit0] MCSVE: Main CSV function enable bit
bit
Description
When 0 is written
The main CSV function is disabled
When 1 is written
The main CSV function is enabled. [Initial value]
When read
The register value is read.
Note:
This register is not initialized by software reset.
To enable sub clock supervisor function, set sub clock oscillation enable setting of system clock mode
control register (SCM_CTL.SOSCE) to “1” and wait until the sub clock oscillation stabilization bit of
system clock mode control register (SCM_STR.SORDY) becomes “1” by stabilized.
The sub clock supervisor function does not operate only by enabling sub clock oscillation of VBAT RTC
(WTOSCCNT.SOSCEX=0).
The following setting combination is prohibited:
− 32 kHz oscillation clock control linkage bit of VBAT RTC sub clock oscillation control register
(WTOSCCNT.SOSCNTL) is “0”.
− 32 kHz oscillation enable bit of VBAT RTC sub clock oscillation control register
(WTOSCCNT.SOSCEX) is “1”.
− Sub clock oscillation enable setting bit of system clock mode control register (SCM_CTL.SOSCE)
is “1”.
− Sub CSV function enable bit of CSV control register (CSV_CTL.SCSVE) = “1”.
For details on VBAT RTC, see "VBAT Domain".