CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 423
4.32 IRQ092/093/094/095 Batch Read Register (IRQxxxMON)
The IRQ092MON to IRQ095MON Registers can read out at once the interrupts (external pin interrupt
ch.16 to ch.31, GDC) assigned to exception no. 108 to no. 111 respectively.
Register configuration
Register function
[bit31:9] Reserved: Reserved bits
A reserved bit reads 0.
[bit8] GDCINT
Register by has the following features. Other than the following becomes a reserved bit “0” is read.
[bit7:4]
Reserved:
Reserved bits
A reserved bit reads
0.
[bit3:0] EXTINT
There is no interrupt request of the external pin interrupt channel corresponding
to the IRQxxxMON Register.
An interrupt request of the external pin interrupt channel corresponding to the
IRQxxxMON Register has been made.
There is no interrupt request of the external pin interrupt channel corresponding
to the IRQxxxMON Register.
An interrupt request of the external pin interrupt channel corresponding to the
IRQxxxMON Register has been made.
There is no interrupt request of the external pin interrupt channel corresponding
to the IRQxxxMON Register.
An interrupt request of the external pin interrupt channel corresponding to the
IRQxxxMON Register has been made.
There is no interrupt request of the external pin interrupt channel corresponding
to the IRQxxxMON Register.
An interrupt request of the external pin interrupt channel corresponding to the
IRQxxxMON Register has been made.
See Table 3-1 and Table 3-2 for the relationship between exception no. and interrupt.
There is no interrupt request of the GDC CommandSequencer.
An interrupt request of the GDC CommandSequencer has been made.
There is no interrupt request of the GDC BlitEngine.
An interrupt request of the GDC BlitEngine has been made.
There is no interrupt request of the GDC DrawingEngine.
An interrupt request of the GDC DrawingEngine has been made.
There is no interrupt request of the GDC ContentStream0.
An interrupt request of the GDC ContentStream0 has been made.