Cypress FM4 Series - Power down Count Register (PWRDWN)

CHAPTER 14: External Bus Interface
826 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.7 Power Down Count Register (PWRDWN)
The PWRDWN register set the count value required for SDRAM to transfer to power down mode..
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial Value
-
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
PDC
Attribute
R/W
Initial Value
0000000000000000
[bit31:16] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit15:0] PDC: Power Down Count
These bits set the count value required for SDRAM to transfer to power down mode.
When the access to SDRAM is implemented in the cycle (MSDCLK) specified with these bits, the mode is
transferred to the power down mode.
bit
Description
0x0000
0 cycles [Initial Value]
…
…
0x8000
32768 cycles
…
…
0xFFFF
65535 cycles