Cypress FM4 Series - IRQ112 Batch Read Register (IRQ112 MON)

CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 425
4.34 IRQ112 Batch Read Register (IRQ112MON)
The IRQ112MON Register can read out at once the interrupts (DSTC transfer end interrupts of I
2
S,
Hi-Speed Quad SPI, Programmable CRC, CAN-FD) assigned to exception no. 128.
Register configuration
bit
31
10
9
8
Field
Reserved
GQSPIDINT
Attribute
R
R
Initial value
0000000000000000000000
00
bit
7
6
5
4
3
2
1
0
Field
I2S1DINT
CANDINT
PCRCDINT
QSPIDINT
I2SDINT
Attribute
R
R
R
R
R
Initial value
00
0
0
00
00
Register function
[bit31:10] Reserved: Reserved bits
A reserved bit reads 0.
[bit9:8] GQSPIDINT
bit
Value
Description
1
0
There is no DSTC transfer end interrupt of GDC HS-SPICNT(data transmission).
1
An interrupt request of DSTC transfer end interrupt of GDC HS-SPICNT(data
transmission) has been made.
0
0
There is no DSTC transfer end interrupt of GDC HS-SPICNT(data reception).
1
An interrupt request of DSTC transfer end interrupt of GDC HS-SPICNT(data
reception) has been made.
[bit7:6] I2S1DINT
bit
Value
Description
1
0
There is no DSTC transfer end interrupt of I
2
S ch.1 (data transmission).
1
An interrupt request of DSTC transfer end interrupt of I
2
S ch.1 (transmission) has
been made.
0
0
There is no DSTC transfer end interrupt of I
2
S ch.1 (data reception).
1
An interrupt request of DSTC transfer end interrupt of I
2
S ch.1 (data reception)
has been made.
[bit5] CANDINT
Value
Description
0
There is no DSTC transfer end interrupt of CAN-FD.
1
An interrupt request of DSTC transfer end interrupt of CAN-FD has been made.