Cypress FM4 Series - Overview of External Bus Interface

CHAPTER 14: External Bus Interface
756 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Overview of External Bus Interface
This section explains an overview of the external bus interface.
The external bus interface allows connections with SRAM/Flash memory/SDRAM outside of the device.
External Bus Interface Features
The features of the external bus interface across the products are as follows:
− Supports connections with 8-bit/16-bit wide SRAM/NOR Flash memories/NAND Flash memories.
Normal SRAM accesses are used for accessing the NOR Flash memories but special pins are
available for accessing the NAND Flash memories.
− Up to 8 chip select signals are available. One chip select signal is provided to SDRAM exclusively.
Address and access timing parameters can be separately set for each chip select signal.
− Up to 25 bits address can be output.
− Supports NOR Flash memory page read.
− Byte lane is fixed to little endian.
− When the access width from CPU and the external bus width are different, the bus size will
automatically be converted.
− Separate mode and multiplex mode are supported for bus accesses. The page read of NOR flash
memory, NAND flash memory, and SDRAM do not support multiplex mode.
− The access timing parameter of ALE signal is added to support the multiplex mode. In addition,
more detailed parameter settings, such as CS assert timing, are possible.
− Clock output feature allows synchronous accesses with target devices.
− Supports external RDY feature.
− Supports SDRAM power down mode.
− It will operate with a division clock output of the base clock (HCLK).
− When MCLKOUT and MSDCLK are to be output from this LSI, it is necessary to configure a division
ratio that satisfies the output standard described on the data sheet.
Notes:
− The bit width to be connected to SARAM, Flash memory, and SDRAM differs depending on
products. For details, see “Data Sheet” of the product used. The further description explains
16-bit width mode.
− For the output standard of the clock signal for synchronous access, refer to External Bus Timing
External Bus Clock Output Standard for the AC timing on Data Sheet of the product to be used.