Cypress FM4 Series - Page 757

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 757
Access Timing and AC Specifications
 Asynchronous Accesses
The external bus interface performs read data latching to the timing of the output enable (MOEX) signal in
reading data. Make the target device to perform the write data latching to the timing of the write enable
(MWEX) signal in writing data. An example of the asynchronous access is shown in Figure 1-1.
Figure 1-1 Asynchronous Access
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[31:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
MCLK
(MCLKOUT)
 Synchronous Accesses
The external bus interface performs read data latching synchronized with the clock output in reading data.
Make the target device to perform the write data latching synchronized with the clock output in writing
data. An example of the synchronous access is shown in Figure 1-2.
Figure 1-2 Synchronous Access
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[31:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
MCLK
(MCLKOUT)
Note:
− See Data Sheet of the product used for details of the AC specifications.