Cypress FM4 Series - Clock Generation Unit Operations; Selecting the Clock Mode

CHAPTER 2-1: Clock
44 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3. Clock Generation Unit Operations
This section explains the clock generation unit.
3.1 Selecting the Clock Mode
Definition of Clock Mode (Selecting the Master Clock)
The MCU clock mode is defined by the source clock selected by the system clock mode control register.
Five types of clock modes are provided: Main clock mode, sub clock mode, high-speed CR clock mode,
low-speed CR clock mode, and main PLL clock mode.
 Main clock mode
In main clock mode, the main clock (CLKMO) is used as a master clock. The clock runs a bus clock used
to operate the CPU, and most peripheral functions.
Status of the PLL clock (CLKPLL) differs depending on the setting of the PLLE bit in the System Clock
Mode Control Register (SCM_CTL), and the sub clock (CLKSO) depends on the SOSCE bit in the
System Clock Mode Control Register (SCM_CTL). The high-speed CR clock (CLKHC) and low-speed CR
clock (CLKLC) cannot be stopped by user program.
 Sub-clock mode
In sub clock mode, the sub clock (CLKSO) is used as a master clock. The clock runs a bus clock used to
operate the CPU, and most peripheral functions.
The main clock (CLKMO), high-speed CR clock (CLKHC), and main PLL clock (CLKPLL) are stopped by
hardware. The low-speed CR clock (CLKLC) cannot be stopped by user program.
 High-speed CR clock mode
In high-speed CR clock mode, the high-speed CR clock (CLKHC) is used as a master clock. The clock
runs a bus clock used to operate the CPU, and most peripheral functions.
Statuses of the main clock (CLKMO), main PLL clock (CLKPLL), and sub clock (CLKSO) differ depending
on the settings of MOSCE, PLLE, and SOSCE bits in the System Clock Mode Control Register
(SCM_CTL). The high-speed CR clock (CLKHC) and low-speed CR clock (CLKLC) cannot be stopped by
user program.
 Low-speed CR clock mode
In low-speed CR clock mode, the low-speed CR clock (CLKLC) is used as a master clock. The clock runs
a bus clock used to operate the CPU, and most peripheral functions.
In low-speed CR clock mode, the main clock (CLKMO), high-speed CR clock (CLKHC), and main PLL
clock (CLKPLL) are stopped by hardware. Status of the sub clock (CLKSO) differs depending on the
setting of the SOSCE bit in the System Clock Mode Control Register (SCM_CTL).
 Main PLL clock mode
In main PLL clock mode, the main PLL clock (CLKPLL) is used as a master clock. The clock runs a bus
clock used to operate the CPU, and most peripheral functions.
Status of the sub clock (CLKSO) differs depending on the setting of the SOSCE bit in the System Clock
Mode Control Register (SCM_CTL). The high-speed CR clock (CLKHC) and low-speed CR clock
(CLKLC) cannot be stopped by user program.