Cypress FM4 Series - Page 43

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 43
Figure 2-2 Block Diagram of Clock Generation Unit (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4)
CPU
FCLK
SLEEPING
/
EN
CLKPLL
CLKMO
CLKHC
CLKSO
CLKLC
CLKPLL
PLL
Analog
reg
*3
FB
X0A
X1A
SWDOGCLK
reg
*2
X1
X0
PLL
OUT
PLL
IN
HCLK
PCLK1
PCLK2
Cortex – M4F
USB clock /
USB / Ethernet clock /
I2S clock
USB / Ethernet clock
CAN prescaler clock
K frequency
division
N frequency
division
M frequency
division
Master clock
*4
Main
oscillation
circuit
High-speed
CR oscillation
circuit
Sub
oscillation
circuit
VBAT domain
*1
Low-speed
CR Ocillation
circuit
Low-speed
CR Ocillation
circuit
Source clock
DIV1 to 16
frequency
division
(default1)
Base clock (HCLK)
TPIU clock (TPIUCLK)
PCLK0
DIV1 to 8
frequency
division
(default1)
DIV1 to 8
frequency
division
(default1)
DIV1 to 8
frequency
division
(default1)
DIV1 to 8
frequency
division
(default1)
DIV1 to 8
frequency
division
(default1)
GDC clock
CLK
GEAR
*1: For details on VBAT Domain, see Chapter VBAT Domain.
*2: PSW_TMR:PINC (PLL input clock select bit)
*3: SCM_CTL:RCS[2:0] (Master clock switch control bits)
*4: The master clock frequency should not be larger than the maximum frequency of base clock (HCLK /FCLK).
For the maximum frequency of base clock (HCLK/FCLK), see Data Sheet of the product used.