CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 545
4.3 Transfer Operation Example 3
This section describes transfer operation example 3. Transfer operation example 3 is an example on
using the Chain Start of the succeeding DES.
DES Values at Transfer Start
In transfer operation example 3, the DSTC uses the Chain Start to re-arrange data at 0x0000 to 0x00FF
and transfer data to the area between 0x0100 and 0x01FF. Four DES are used in this example. The first
DES is called 1st-DES, the second DES 2nd-DES, the third DES 3rd-DES and the fourth DES 4th-DES.
Table 4-5 shows the respective details of the four DES. There is no DES4 in each DES. The respective
addresses of the four DES are not shown in Table 4-5. However, allocate the four DES next to each other
in sequence from 1st-DES to 4th DES on the memory.
Table 4-5 DES Values at Transfer Start in Transfer Operation Example 3
DES0 = 0x702090C3
DV = 11 : No DES close process to be executed at the end of transfer
MODE = 0, TW = 00 : Mode 0, 8-bit (byte) transfer
ORL = 110 : OuterReload of DES2 <= DES5, DES3 <= DES6
SAC = 100 : Increment of TW×4 without InnerReload
DAC = 100 : Increment of TW×4 without InnerReload
CHRS = 100000 : There is a Chain Start in the succeeding DES; no interrupt flag
has been set.
DMSET = 0 : Set DMSET to "0" as the transfer is an SW Transfer.
CHLK = 0 : No Chain lock
ACK = 00 : Set ACK to "00" as the transfer is an SW Transfer.
PCHK = 0111 : Parity
ORM = 0x0001, IIN = 0x0040
DES5 has the same values as DES2 of 1st-DES, and DES6 as DES3 of
1st-DES.
DES5 has the same values as DES2 of 2nd-DES, and DES6 as DES3 of
2nd-DES.
DES5 has the same values as DES2 of 3rd-DES, and DES6 as DES3 of
3rd-DES.
DES0 = 0x401090C3
CHRS = 010000 : There is no Chain Start; an interrupt flag has been set.
PCHK = 0100 : Parity
Other values are the same as those of DES0 of 1st-DES.
DES5 has the same values as DES2 of 4th-DES, and DES6 as DES3 of
4th-DES.
Transfer Operation Flow
Figure 4-3 shows the transfer operation flow in transfer operation example 3. The Start Trigger of (A) in
the Figure 4-3 shows write accesses to the DESP of 1st-DES to the SWTR Register from the CPU. The
Start Triggers of (B), (C) and (D) in the Figure 4-3 are Chain Start Triggers.