Cypress FM4 Series - Peripheral Function Reset Control Register 1 (MRST1)

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 99
4.4 Peripheral Function Reset Control Register 1 (MRST1)
This section explains the peripheral function reset control register 1(MRST1).
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
QDURST[3:0]
Attribute
-
R/W
Initial value
-
0000
bit
15
14
13
12
11
10
9
8
Field
Reserved
MFTRST[3:0]
Attribute
-
R/W
Initial value
-
0000
bit
7
6
5
4
3
2
1
0
Field
Reserved
BTMRST[3:0]
Attribute
-
R/W
Initial value
-
0000
[bit31:20] Reserved: Reserved bits
Write "0" to these bits.
[bit19:16] QDURST[3:0]: Reset control of quad counter
These bits control the reset of each unit of the quad counter. The correspondence between each bit and
the quad counter unit is shown below.
bit16 - QDURST 0: Quad counter unit 0
bit17 - QDURST 1: Quad counter unit 1
bit18 - QDURST 2: Quad counter unit 2
bit19 - QDURST 3: Quad counter unit 3
If the relevant bit is set to 1, the unit of the corresponding quad counter becomes a reset state, the quad
counter operation stops, and the register settings are initialized. For products to which the relevant quad
counter is not mounted, do not change the relevant bit from the initial state. To release the reset state, be
sure to set this bit to 0 again.
bit
Description
0
Releases the reset of the quad counter corresponding to the relevant bit. (Initial value )
1
Issues the reset to the quad counter unit corresponding to the relevant bit.
[bit15:12] Reserved: Reserved bits
Write 0 to these bits.