Cypress FM4 Series - External Interrupt Factor Register (EIRR)

CHAPTER 9: External Interrupt and NMI Control Sections
446 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.2 External Interrupt Factor Register (EIRR)
The EIRR register indicates that an external interrupt request is detected.
Register configuration
bit
31
16
Field
ER[31:16]
Attribute
R
Initial value
0xXXXX
bit
15
0
Field
ER[15:0]
Attribute
R
Initial value
0xXXXX
Register functions
[bit31:0] ER31 to ER0: External interrupt request detection bits
ER31 to ER0 bits correspond to pins INT31 to INT00.
The bit corresponding to a pin that is not defined in the product specifications is indefinite.
bit
Function
0
Detects no external interrupt request of INTx pin corresponding to the relevant bit.
1
Detects an external interrupt request of INTx pin corresponding to the relevant bit.
Writing
No effect on operation
Notes:
− When level detection is set with ELVR and while valid level is input from INTxx pin, clearing
applicable bit (write 0) with the External Interrupt Factor Clear register (EICL) will reset 1 to
applicable bit in the External Interrupt Factor Register (EIRR).
− As the initial values of GPIO are set to general purpose ports, applicable bit in the External
Interrupt Factor Register (EIRR) may be set to 1. After set the GPIO to external interrupt pin,
clear the External Interrupt Factor Register (EIRR).