Cypress FM4 Series - Usage Precautions

CHAPTER 3: Clock Supervisor
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 157
7. Usage Precautions
 This section explains the precautions for using the clock supervisor functions.
For details on enabling and clearing the frequency detection interrupt sources, see Chapter "Clock".
 For details on clock failure detection and anomalous frequency detection reset sources, see Chapter
"Resets".
 Operation after the occurrence of a reset
After the occurrence of a reset triggered by clock failure detection, clock mode returns to high-speed CR.
Do not select the faulty clock again.
 The high-speed CR clock for use of the frequency detection
The frequency failure detection is affected by the frequency accuracy of high-speed CR itself.
When you configure frequency window, therefore, the accuracy of high-speed CR must be considered for
the window value. Do not trim the high-speed CR clock after the anomalous frequency detection has
been enabled.
 The order of the anomalous frequency detection settings before using
Before enabling FCS (FCSDE=1), specify the count cycle (FCD), reset enable (FCSRE), and frequency
window (FWH/FWL) settings.
If you want to change any of FCD/FCSRE/FWH/FWL after FCS has been enabled, stop the FCS function
before changing the setting. Do not change the setting while FCS is enabled.
 The enable settings of the anomalous frequency detection before using
Depending on the setting of the FCSRE bit in the CSV control register (CSV_CTL), operation during
anomalous frequency detection varies. Table 7-1 shows the setting list.
Table 7-1 List of the FCS Function and FCSRE bit Settings
FCSRE=0
FCSRE=1
FCSDE=0
Stops FCS function
Stops FCS function
FCSDE=1
Enables FCS function
Generates an interrupt upon error detection
Enables FCS function
An interrupt occurs upon the first error detection
A reset occurs upon the second error detection
 Interrupt settings for the frequency detection and main timer mode
The internal bus clock stops while the clock mode is in main timer mode. In this mode, an interrupt does
not occur even if an error is detected while FCSRE is set to "0".
In main timer mode, therefore, do not set FCSRE bit to "0". If FCSRE bit is set to "1", a reset occurs upon
the second error detection.
 The settings for CSV OFF and external reset.
When CSV function is set to OFF, the CSV reset is not generated if the clock failure occurs.
The external reset (INITX) is not also accepted if the clock failure occurs. So, it is recommended not to
turn OFF the CSV function, if you do not have special reason.