Cypress FM4 Series - SDRAM Mode Register (SDMODE)

CHAPTER 14: External Bus Interface
820 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.5 SDRAM Mode Register (SDMODE)
This section explains the configuration of SDMODE.
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
MSDCLK
OFF
Attribute
-
R/W
Initial value
-
0
bit
15
14
13
12
11
10
9
8
Field
BASEL
RASEL
Attribute
R/W
R/W
Initial value
0001
0011
bit
7
6
5
4
3
2
1
0
Field
Reserved
CASEL
Reserved
ROFF
PDON
SDON
Attribute
-
R/W
-
R/W
R/W
R/W
Initial value
-
00
-
0
0
0
[bit31:17] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit16]MSDCLKOFF: MSDCLK OFF
This bit sets the output of the clock for SDRAM (MSDCLK).
This bit stops the lock for SDRAM (MSDCLK). This is independent from the state of SDON. Therefore,
when this bit set to 1 at SDON=1, the clock supply to SDRAM is stopped and the access is disabled.
bit
Description
0
Outputs the clock for SDRAM (MSDCLK) [Initial value]
1
Dose not output the clock for SDRAM (MSDCLK).
[bit15:12]BASEL: Bank Address Select
These bits select the address bit on the internal bus output as address bank.
bit
Description
0000
MAD[15:14] = Internal address[20:19]
0001
MAD[15:14] = Internal address [21:20] [Initial value]
0010
MAD[15:14] = Internal address [22:21]
0011
MAD[15:14] = Internal address [23:22]
0100
MAD[15:14] = Internal address [24:23]
0101
MAD[15:14] = Internal address [25:24]
0110
MAD[15:14] = Internal address [26:25]
0111 to 1111
Setting is prohibited.