Cypress FM4 Series - Memory Controller Register (MEMCERR)

CHAPTER 14: External Bus Interface
832 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.10 Memory Controller Register (MEMCERR)
The MEMCERR register enables SDRAM/Flash memory/SDRAM error interrupt.
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial Value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial Value
-
bit
15
14
13
12
11
10
9
8
Field
Reserved
Attribute
-
Initial Value
-
bit
7
6
5
4
3
2
1
0
Field
Reserved
SDION
SFION
SDER
SFER
Attribute
-
R/W
R/W
R/W
R/W
Initial Value
-
0
0
0
0
[bit31:4] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit3] SDION: SDRAM error Interrupt ON
Enables an interrupt for SDRAM error.
bit
Description
0
Disables SDRAM error interrupt.
1
Enables SDRAM error interrupt.
[bit2] SFION: SRAM/Flash error Interrupt ON
Enables an interrupt for SRAM /Flash memory error.
bit
Description
0
Disables SRAM/Flash memory error interrupt.
1
Enables SRAM/ Flash memory error interrupt.
[bit1] SDER: SDRAM Error
This bit is used to indicate that the access to SDRAM area is executed in the condition where SDON=1 is
not set in SDRAM mode register (SDMODE). At this time, the external bus interface returns an error
response to the internal bus and sets this register at the same time. This bit is cleared by writing 1.
bit
Description
0
No SDRAM error exists.
1
SDRAM error exists.