Cypress FM4 Series - Low-Speed CR Prescaler Operation and Setup Procedure Example

CHAPTER 2-4: Low-Speed CR Prescaler
134 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3. Low-speed CR Prescaler Operation and Setup Procedure Example
This section explains the operation of Low-speed CR Prescaler. This section also shows the example of
setup procedures.
Setup Procedures of Low-speed CR Prescaler
The Low-speed CR is asynchronous with the peripheral clock (PCLK).
For writing to the Low-speed CR Prescaler Reload Register, the peripheral clock is used. Therefore, if the
setting change of the Low-speed CR Prescaler Load Register and the reload of the reload counter occur
simultaneously, a value reloaded to the reload counter is not guaranteed.
So, execute the rewriting of the Low-speed CR Prescaler Reload Register conforming to the following
procedures.
 For Switching the division clock
The initial value of the Low-speed CR Prescaler Reload Register(LCR-PRSLD) is 0.
Thus, for changing the value from the initial value, these procedures are unnecessary.
1. Set "0" to the Low-speed CR Prescaler Reload Register (LCR_PRSLD).
2. Wait until the value of the Low-speed CR Prescaler Reload Register (LCR_PRSLD) is reloaded to the
reload counter.
3. The wait time is obtained by calculating the following formula:
Low-speed CR cycle (50 kHz: 20 µs)  the set value before changed to 0 in Item 1.
4. Write new setup value to the Low-speed CR Prescaler Reload Register (LCR_PRSLD).
For wait time at setup change, see Table 3-1.
Table 3-1 Setup Wait Time
Reload Value
before Setup
Setup
Value
Wait Time
0
0
Not exists.
1
0
20 µs (20 µs  1)
2
0
40 µs (20 µs  2)
3
0
60 µs (20 µs  3)
:
:
:
60
0
1200 µs (20 µs  60)
61
0
1220 µs (20 µs  61)
62
0
1240 µs (20 µs  62)
63
0
1260 µs (20 µs  63)
Notes:
− The division clock cannot be stopped.
− The setting of the Low-speed CR Prescaler Reload Register (LCR_PRSLD) is executed at the
underflow of the Low-speed CR Reload Counter.