CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 465
3.4 Hardware-Block Transfer & Burst Transfer
This section explains Hardware-Block transfer and Burst transfer.
Hardware-Block transfer or Hardware-Burst transfer is used when performing DMA transfer by the
transfer request signal from the Peripheral of the base timer or external interrupt.
Hardware-Block transfer and Hardware-Burst transfer are methods used to receive the transfer request
signal at the rising edge of the signal. Transfer is executed, when the rising edge of the transfer request
signal is detected. DMAC’s transfer start timing can be specified by the output of the interrupt signal from
each Peripheral.
Figure 3-4 shows an example of the operation of Hardware-Block transfer. In this example, the following
settings apply. The settings of the addresses of the transfer source and transfer destination as well as the
transfer data width are omitted.
− Transfer mode: Hardware-Block transfer
(ST=0, IS= Peripheral at the transfer request source, MS=00)
− Transfer data size: Number of blocks = 4, Number of transfers = 3 (BC=3, TC=2)
Figure 3-4 Example of Operation of Hardware-Block Transfer
The operation of Hardware-Block transfer is as follows:
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits for a
transfer request from the Peripheral. After receiving the transfer request, it performs transfers for the
number of blocks (=BC+1) and then waits for the next transfer request. During the wait period, a Transfer
Gap is generated. Every time a transfer request is received, it performs the same operation for the
number of transfers (TC+1). The total number of transfers to be performed is (BC+1) (TC+1). Match the
number of transfer requests from the Peripheral and the number of DMAC transfers (TC+1). Once all of
the transfers are completed, DMAC notifies CPU of the completion.
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