CHAPTER 10: DMAC
466 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 3-5 shows an example of the operation of Hardware-Burst transfer. In this example, the following
settings apply. The settings of the addresses of the transfer source and transfer destination as well as the
transfer data width are omitted.
− Transfer mode: Hardware-Burst transfer
(ST=0, IS= Peripheral at the transfer request source, MS=01)
− Transfer data size: Number of blocks =4, Number of transfers = 5 (BC=3, TC=4)
Figure 3-5 Example of Operation of Hardware-Burst Transfer
The operation of Hardware-Burst transfer is as follows:
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits for a
transfer request from the Peripheral. After receiving the first transfer request, it performs all of the
transfers for the number of times calculated by (BC+1)×(TC+1). During the Hardware-Burst transfer, no
Transfer Gap is generated. Once all of the transfers are completed, DMAC notifies CPU of the
completion.
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