CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 507
2.2 DSTC and System Configuration
Figure 2-2 shows the block diagram illustrating the DSTC and system configuration.
Figure 2-2 Block Diagram of DSTC and System Configuration
DREQ[255:0]
DSTC
DSTC system bus (AHB/Peripheral)
Peripheral
( Hardware DMA available )
Interrupt / Transfer req.
Combined Type
CPU
Peripheral
( Hardware DMA unavailable )
Flash
NVIC
Interrupt
CPU system bus (AHB/Peripheral)
RAM
DES area
max. 1024
HWINT[255:0]
SWINT, ERINT
Output:
Hardware transfer end
interrupt
Output:
Software transfer interrupt
Transfer error interrupt
Input:
DMA transfer request
Output:
DMA request enalbe
DREQENB[255:0]
Peripheral
( Hardware DMA available )
Interrupt / Transfer req.
Separated Type
Transfer
request
Interrupt/
Transfer
request
1
0
SEL3
SEL2
Connection with System
The system configuration diagram in Figure 2-2 has been simplified to facilitate explanation. For details of
the system configuration, refer to chapter System Overview in Peripheral Manual. The DSTC is
connected to the CPU, Flash, RAM and peripherals via the system bus. The DSTC has a dedicated bus,
which is independent of the CPU bus, and has a configuration enabling it to execute a transfer operation
when the CPU bus is being accessed. The DSTC accesses any address area on the system according to
the specified transfer destination address and transfer source access of a channel, and executes data
transfer between the memory and a peripheral. The DSTC cannot access certain areas. Refer to the
memory map to check which areas the DSTC cannot access.
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