CHAPTER 11: DSTC
508 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
DREQENB[n] Register and Connection with DREQ[n] Signal and HWINT[n] Signal
The DSTC supports up to 256 hardware transfer request signal inputs. The interrupt signal from a
peripheral supporting DSTC hardware transfer is connected to the DSTC. The DSTC can start a transfer
operation with the interrupt signal from a peripheral as a DMA transfer request signal (DREQ[255:0]). The
DSTC cannot start the DMA transfer of the DSTC with an interrupt signal from a peripheral not supporting
DSTC hardware transfer. In the case of a peripheral having multiple channels and multiple interrupt
sources, there are interrupts supporting and those not supporting the DMA transfer.
The settings of the DREQENB[255:0] determine whether hardware transfer requests from peripherals are
valid. The specifications of the product equipped with the DSTC determine which bit out of 256 bits
supports the interrupt signal of which peripheral. For details, see Chapter: Interrupts.
There are two types of peripheral functions using DMA transfer of DSTC; one is the interrupt signal and
DMA transfer request signal is combined for sharing use,( This is abbreviated “Combined type”.) and
another is handling them separately.(This is abbreviated “Separated type”.) The setting value of the
DREQENB[255:0] register and the SE2, SEL3 in this figure switch the operations as follows.
Case of the Combined type:
When DREQENB[n]=0;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is ignored by the DSTC.
HWINT[n] signals from DSTC are not inputted to NVIC. HWINT[n] is the output signal for interrupt
from the DSTC to the CPU, and is used to for notification of a HW transfer completion of the
DSTC.
When DREQENB[n]=1;
Interrupt signal from peripheral is not inputted to the NVIC.
Interrupt signal from peripheral is inputted to the DSTC, and the DSTC start the DMA transfer by
this signals.
HWINT[n] signals from DSTC are inputted to NVIC, instead of interrupt signal from peripheral.
In the case of this type, the input port of NVIC is shared to use the interrupt from peripheral and HWINT[n]
interrupt of the transfer completion from the DSTC. With this configuration, in the process of the NVIC, an
interrupt from a peripheral, and a transfer completion interrupt from the DSTC jump to the same interrupt
vector. Therefore, use the DREQENB[n] register to choose the interrupt to be processed.
Case of the Separated type:
When DREQENB[n]=0;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is not inputted to the DSTC.
Transfer request signal from peripheral is not inputted to the NVIC
Transfer request signal from peripheral is ignored by the DSTC
HWINT[n] from the DSTC is inputted to the NVIC. (not asserted ).
When DREQENB[n]=1;
Interrupt signal from peripheral is inputted to the NVIC, notify interrupt.
Interrupt signal from peripheral is not inputted to the DSTC.
Transfer request signal from peripheral is not inputted to the NVIC
Transfer request signal from peripheral is inputted to the DSTC, start the transfer.
HWINT[n] from the DSTC is inputted to the NVIC, notify transfer completion.
In the case of this type, the input port of NVIC is separated the interrupt from peripheral and HWINT[n]
interrupt of the transfer completion from the DSTC. In the process of the NVIC, an interrupt from a
peripheral, and a transfer completion interrupt from the DSTC does not jump to the same interrupt vector.
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