CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 509
For details of peripheral types, refer to the list of interrupts and the list of interrupt signals input to DSTC in
the Interrupts chapter.
Connection to Hardware Transfer Request Clear Signal
Among peripherals supporting the hardware transfer, there are some for which a transfer request signal
(interrupt signal) has to be cleared after a transfer has ended. Though the clearing process is not
mentioned in Figure 2-2, if the interrupt request signal of such peripheral is enabled by its corresponding
DREQENB[n] register, the transfer request signal is cleared by the DSTC.
Connection to Hardware Transfer Stop Request Signal
The Multi-Function Serial Unit (to be called MFS later in this document) output signal for DMA transfer
stop request. Though it is not mentioned in Figure 2-2, if the transfer stop request signal from these has
been asserted, the transfer request signal is masked. Therefore, the DSTC does not perform the DMA
transfer in the state of waiting for the DMA request signal, and no error response is generated from the
DSTC.
Conditions that are asserted by MFS's transfer stop request signal show below.
− If received interrupts are enabled (SCR:RIE=1), a received interrupt occurs (SSR:PE bit, FRE bit, or
ORE bit is set to 1).
− If chip select error interrupt are enabled (SACSR:CSEIE=1), a chip select error interrupt occurs
(SACSR:CSE bit is set to 1).
Separately, the transfer stop request signal from MFS is sent to the CPU via NVIC as an interrupt.
Terminate this current DMA transfer of the DSTC by the CPU with this interrupt. For details, see Chapter:
Interrupts.
Interrupt Signal from DSTC
The transfer end interrupt for a transfer started by a software start is sent to the NVIC by the SWINT. The
error interrupt generated due to the occurrence of a transfer error is sent to the NVIC by the ERINT.
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