Cypress FM4 Series - SDRAM Access

CHAPTER 14: External Bus Interface
782 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.9 SDRAM Access
This section explains SDRAM access.
Memory Access
In SDRAM access, MCSX[8] address output determines the target device. Then, by outputting MRASX/
MCASX/MSDWEX/MSDCKE , read/write operation is executed to the target device.
Pins Used
For SDRAM access, use the pins in Table 3-8.
Table 3-8 External Interface Pins for SDRAM Memory
Pin Names
Functions
MAD[24:0]
Address output pins
MADATA[31:0]
Data input/output pins
MCSX[8]
Chip selection pins
MDQM[3:0]
Byte mask signal output pins
MRASX
Row address strobe output pin
MCASX
Column address strobe output pin
MSDWEX
Write enable output pin
MSDCKE
Clock enable output pin
MSDCLK
Clock output pin
Notes:
− Depending on the settings and the target device,(NAND Flash memory), all pins in Table 3-8 are
not used.
− The external bus interface pins that appear are different by the product. For details, see Data
Sheet of the product used.
− For SDRAM access, Multiplex mode is not available.
Target devices can be operated with the following combinations by SDRAM access.
Table 3-9 SDRAM Access Signal Combinations
Function
MCSX[8]
MRASX
MCASX
MSDWEX
MDQM
MAD
MADATA
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (ACT)
L
L
H
H
X
Bank/Row
X
READ (READ)
L
H
L
H
L/H
Bank/Col
X
WRITE (WRIT)
L
H
L
L
L/H
Bank/Col
Valid
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (PRE)
L
L
H
L
X
Code
X
AUTO REFRESH (REF)
or SELF REFRESH (SREF)
L
L
L
H
X
X
X
LOAD MODE REGISTER (MRS)
L
L
L
L
X
Op-Code
X
Write Enable/Output Enable
-
-
-
-
L
-
Active
Write Inhibit/Output High-Z
-
-
-
-
H
-
High-Z