Cypress FM4 Series - Page 783

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 783
SDRAM Read Access
For the operation example of SDRAM read access, see Figure 3-19.
Figure 3-19 SDRAM Read Access
0 1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18
MSDWEX
MRASX
MCASX
MCSX[8]
MADATA[15:0]
MAD[15:0]
MSDCLK
RA
D0 D1
TREFC=2
TRCD=0
TRAS=0
CL=1
TRP=0
ACTNOPNOP READ READ READ
READ
READ PRE NOP NOP ACT READ READ READ
READ
PRE
REF
D0
CA0 CA1 RA CA0
CPU Word access
CPU Half Word access
CPU Byte access
Read 32-bit data
Read 8-bit or 16-bit data
Access conditions
− SDRAM 8-/16-/32-bit access
− Number of CAS latency cycles (SDTIM:CL): 0b01 (2 cycles)
− Number of RAS precharge time cycles (SDTIM:TRP): 0b0000 (1 cycle)
− Number of latency cycles between RAS and CAS (SDTIM:TRCD): 0b0000 (1 cycle)
− Minimum number of row active time cycles (SDTIM:TRAS): 0b0000 (1 cycle)
− Number of command latency cycles following refresh (SDTIM:TREFC): 0b0010 (3 cycles)
RA: Row address
CA: Column address