Cypress FM4 Series - Page 784

CHAPTER 14: External Bus Interface
784 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
SDRAM Write Access
For the operation example of SDRAM read access, see Figure 3-20.
Figure 3-20 SDRAM Write Access
0 1 2 3 4 5 6 7 8 9
10
11 12
MSDWEX
MRASX
MCASX
MCSX[8]
MADATA
MAD
MSDCLK
RA
D0 D1
TREFC=2
TRCD=0
TRAS=0
TDPL=0
TRP=0
REF
NOP
NOP
ACT WRIT
WRIT WRIT
PRE
CA0 CA1
RA CA0
D0
NOP
ACT
PRE NOP
CPU Word access
Write 32-bit data
CPU Half Word access
CPU Byte access
Write 8-bit or 16-bit data
Commands
Access conditions
− SDRAM 8-/16-/32-bit access
− Number of CAS latency cycles (SDTIM:CL): 0b01 (2 cycles)
− Number of precharge time cycles (SDTIM:TRP): 0b0000 (1 cycle)
− Number of latency cycles between RAS and CAS (SDTIM:TRCD): 0b0000 (1 cycle)
− Minimum number of row active time cycles (SDTIM:TRAS): 0b0000 (1 cycle)
− Number of command latency cycles following refresh (SDTIM:TREFC): 0b0010 (3 cycles)
− Number of latency cycles until precharge after write (SDTIM:TDPL): 0b00 (1 cycle)
RA: Row address
CA: Column address