CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 785
Power-on Sequence
By changing SDON bit of SDRAM mode register (SDMODE) from 0 to 1, the power-on sequence is
issued and the access to SDRAM is enabled. For the power-on sequence issued, see Figure 3-21. In
Figure 3-21, “cycle” is based on MSDCLK.
Figure 3-21 Power-on Sequence Operation
(*1): The setting of Mode Set are as follows :
BL=1, BT=Seq, CL=SDTIM.CL Register Value, Normal Operation , Programmed Write Burst
(*2): This is the initial cycle count of TREFC .
Before asserting SDON bit, the cycle count can be set with TREFC register.
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