CHAPTER 14: External Bus Interface
786 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Refresh Operation
When ROFF bit of SDRAM mode register (SDMODE) is 0, the refresh is executed with the setting
conditions of Refresh time register (REFTIM). The Refresh time register (REFTIME) can control the
interval and count of the refresh and the preceding refresh.
Refresh Interval
Set the interval to execute refreshes with REFC bit of the Refresh time register (REFTIM). The refresh is
implemented after the set cycle count (MSDCLK) has elapsed. Moreover, set the refresh issuing count in
one refresh timing with NREF bit. The following shows the operation example at the setting of NREF=2. In
Figure 3-22, cycle is based on MSDCLK.
Figure 3-22 Refresh Intervals and Issuing Count
Preceding Refresh
Set the preceding refresh with PREF bit of the Refresh time register (REFTIM). The preceding refresh is
the refresh executed earlier than the actual refresh.
By using the preceding refresh, the access to SDRAM is improved.
For the operation of the preceding refresh, see Figure 3-23. In Figure 3-23, cycle is based on MSDCLK.
− Refreshing is previously executed when SDRAM is not accessed after refreshing is implemented.
(*1 in Figure 3-23)
− After the preceding refresh is executed, if the access to SDRAM is executed in the next refresh
timing, the refresh is not executed. (*2 in Figure 3-23)
− After the access to SDRAM is completed, the preceding refresh is implemented again. (*3 in Figure
3-23)
− When the access to SDRAM is not completed, the refresh is forcibly executed in the third refresh
timing. (*4 in Figure 3-23)
Figure 3-23 Preceding Refresh Operation
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