Cypress FM4 Series - Non Maskable Interrupt Factor Clear Register (NMICL)

CHAPTER 9: External Interrupt and NMI Control Sections
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 451
4.7 Non Maskable Interrupt Factor Clear Register (NMICL)
The NMICL register is used to clear the held interrupt factor.
Register configuration
bit
15
1
0
Field
Reserved
NCL
Attribute
-
R/W
Initial value
-
1
Register functions
[bit15:1] Reserved: Reserved bits
The read value is undefined.
They have no effect in write mode.
[bit0] NCL: NMI interrupt factor clear bit
The NCL bit corresponds to NMIX pin.
bit
Function
When 0 is written
Clears an NMI interrupt factor.
When 1 is written
No effect on operation
Reading
Always reads 1.
Notes:
− If ELVR is rewritten to change the detection condition, an invalid interrupt factor may occur.
To avoid an invalid interrupt factor from occurring, keep the procedure shown in Figure 3-1 when
changing the detection condition.
− To detect the edge or level specified in ELVR, at least 3T (T: PCLK cycle) is required as the pulse
width.
If a signal that does not satisfy the pulse width is input, it is not guaranteed that correct operations
will be carried out.
− When level detection is specified in ELVR, the corresponding bit in the External Interrupt Factor
Register (EIRR) is set to 1 again while the effective level is input from pin INTxx even if the
corresponding bit is cleared (set to 0) with the External Interrupt Factor Clear Register (EICL).
− The NMI detection level setting register is not provided. In normal mode, the falling edge is
detected.
This register is used to return from stop mode when the L level is detected.
− NMI is targeted for non maskable interrupt, so an NMI Enable Interrupt Request Register is not
provided.