Cypress FM4 Series - Peripheral Address Map

CHAPTER 1: System Overview
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 29
1.4 Peripheral Address Map
Table 1-1 shows the peripheral address map.
Table 1-1 Peripheral Address Map
Start Address
End Address
Bus
Access other
than CPU
Peripheral
Register
Map
CHAPTER
0x4000_0000
0x4000_0FFF
AHB
Disabled
FLASH IF Register (Main)/
Unique ID Register
FLASH_IF/
Unique ID
*1
Chapter17
Chapter18
0x4000_1000
0x4000_FFFF
Reserved
-
-
0x4001_0000
0x4001_0FFF
APB0
Disabled
Clock and Reset Control
Clock /
Reset
Chapter 2-1
Chapter 3
Chapter 4
Chapter 6
0x4001_1000
0x4001_1FFF
Hardware Watchdog Timer
HW WDT
Chapter 1 in Timer
Part
0x4001_2000
0x4001_2FFF
Software Watchdog Timer
SW WDT
0x4001_3000
0x4001_4FFF
Reserved
-
-
0x4001_5000
0x4001_5FFF
Dual Timer
Dual_
Timer
Chapter 2 in Timer
Part
0x4001_6000
0x4001_FFFF
Reserved
-
-
0x4002_0000
0x4002_0FFF
APB1
Multi-function Timer unit0
MFT
Chapter 6 in Timer
Part
0x4002_1000
0x4002_1FFF
Multi-function Timer unit1
0x4002_2000
0x4002_2FFF
Multi-function Timer unit2
0x4002_3000
0x4002_3FFF
Reserved
-
-
0x4002_4000
0x4002_4FFF
PPG
PPG
Chapter 7-2 in Timer
Part
0x4002_5000
0x4002_5FFF
Base Timer
Base Timer/
Base Timer
Selector
Chapter 5-1
Chapter 5-2
in Timer Part
0x4002_6000
0x4002_6FFF
QPRC
QPRC
Chapter 8-1
Chapter 8-2 in Timer
Part
0x4002_7000
0x4002_7FFF
A/D Converter
A/DC
Chapter 1-1 Chapter
1-2
Chapter 1-3 in Analog
Macro Part
0x4002_8000
0x4002_DFFF
Reserved
-
-
0x4002_E000
0x4002_EFFF
High speed CR trimming
CR Trim
Chapter 2-3
*1: For the details of Flash IF Register, see Flash Programming Manual of the product used.