Cypress FM4 Series - Setup Procedure Example

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 799
5. Setup Procedure Example
The following explains an example of the external bus interface setup procedure.
Executes external bus interface reset
Access Peripheral Reset Control Register 0 (MRST0) of peripheral clock gating.
- Executes external bus interface reset (EXBRST = 1)
- Releases external bus interface reset (EXBRST = 0)
Settings for MSDCLK output gating.
Access SDRAM Mode Register (SDMODE)
- Set SDRAM clock (MSDCLK) output gating. (MSDCLKOFF = 1)
External bus setup start
Settings for MCLKOUT output gating and division ratio of clock.
Access Division Clock Register (DCLKR)
- Set SRAM/Flash clock (MCLKOUT) output gating. (MCLKON = 0)
- Set the division ratio of MCLKOUT/MSDCLK. (MDIV[3:0])
- Check MCLKON = 0 and MDIV[3:0] = setting value.
Settings for I/O port
Access Extended Pin Function Register (EPFR) of I/O port
- Set pin function setting of external bus interface by EPFR10, EPFR11 and EPFR20.
Setting for MCLKOUT/MSDCLK output
Access Division Clock Register (DCLKR)
- Set SRAM/Flash clock (MCLKOUT) output. (MCLKON=1)
- Check MCLKON = 1.
Access SDRAM Mode Register (SDMODE)
- Set SDRAM clock (MSDCLK) output. (MSDCLKOFF = 0)
Continue to next page