Cypress FM4 Series - Page 800

CHAPTER 14: External Bus Interface
800 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Notes:
− Make sure to set up the division clock while the division clock is stopped.
− Some of setup combinations in the mode register cannot be used at the same time.
Settings for auto wait time
Access Timing Register. (TIM0 to TIM7)
Settings for chip select address
Access Area Register. (AREA0 to AREA7)
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Settings for SDRAM configuration
Access SDRAM Mode Register. (SDMODE)
- Set SDRAM access configuration. (BASEL[3:0], RASEL[3:0], CASEL[1:0], ROFF,
PDON)
Access Refresh Timer Register. (REFTIM)
- Set interval of refresh, number of refresh and pre-refresh. (REFC[15:0], NREF[7:0],
PREF)
Access Power Down Count Register. (PWRDWN)
- Set the count value required for SDRAM to transfer to power down mode. (PDC[15:0])
Access SDRAM Timing Register. (SDTIM)
- Set the latency of SDRAM.
(CL, TRC[3:0], TRP[3:0], TRCD[3:0], TRAS[3:0], TREFC[3:0], TDPL)
Settings for SDRAM access ON
Access SDRAM Mode Register. (SDMODE)
- Set SDRAM access ON. (SDON = 1)
End of setup
When using multiplex mode,
Access ALE Timing Register. (ATIM0 to ATIM7)
Settings for SRAM/Flash memory access mode
Access SRAM/Flash memory Mode Register (MODE0 to MODE7)
- Set bus access mode. (MOEXEUP, MPXCSOF, MPXDOFF, ALEINV, MPXMODE,
SHRTDOUT, WBMON, RBMON, WDTH[1:0])
- Set page access mode (PAGE)
- Set NAND flash memory mode (NAND)